1. Field of the Invention
This invention relates to a method for scrubbing storage in a computer memory, and particularly to a memory scrubbing method which enables the use of a pattern that correlates with physical structures to perform a memory scrubbing operation of a plurality of memory modules, in order to detect errors in the memory modules more quickly, and to perform testing or replacement thereof more efficiently.
2. Description of Background
In memory modules such as dual-in-line memory modules (DIMMs) used in portable electronic devices, for example, mobile phones and portable computers, memory data and keys are periodically scrubbed to correct soft errors, i.e., correctable errors (CEs) before they develop into hard errors, i.e., uncorrectable errors (UEs). Conventionally, each memory module is fully scrubbed in turn, sequentially, one at a time. Thus, this creates a problem in that when one of the memory chips of a memory module includes errors and the erroneous memory chip is located at a non-sequential memory location such that it would take a long time to sequentially scan to arrive to that memory address, the erroneous memory chip may not be found and corrected until the entire memory subsystem has been scrubbed.